Avinash Karanth received his PhD and MS from The University of Arizona in August 2006 and May 2003 respectively. Presently, he is the Chair of the School of Electrical Engineering and Computer Science (EECS) at Ohio University. He is also Joseph K. Jachinowski Professor in the School of EECS where he leads the Technologies for Emerging Computer Architecture Laboratory (TEAL) at Ohio University. His research interests include Computer Architecture, Machine Learning, Hardware Accelerators, Network-on-Chips (NoCs), Emerging Technologies (nanophotonics, wireless), Hardware Security, and Exascale Networks.
Avinash Karanth has received the prestigious NSF CAREER Award in 2011, Presidential Research Scholar Award in 2017, Best Paper Award at the ICCD 2013 conference and his papers have been nominated for Best Paper at IEEE Design and Test in Europe (DATE) in 2019, IEEE Symposium on Network-on-Chips (NoCs) in May 2010 and IEEE Asia & South Pacific Design Automation Conference (ASP-DAC) in January 2009. His research has been sponsored by National Science Foundation (NSF), Air Force Research Lab (AFRL), Ohio Department of Higher Education (ODHE) and Advanced Micro Devices (AMD) grants. Further, he has published 100+ articles in peer-reviewed IEEE and ACM journals and conferences.
He is an Associate Editor for IEEE Transactions on Computers and IEEE Transactions on Cloud Computing and he has been a co-Guest Editor for IEEE Transactions on Emerging Topics for Computing ('15-'16) and Journal of Parallel and Distributed (JPDC) ('10-'11). He was the co-Chair of the architecture track at IPDPS-2020 and vice-Chair of the EDA track at DAC-2021 and DAC-2022 conferences. He has served on the Program Committee of HPCA (2019), DAC (2018-19), NoCs (2016-19), MPSoC (2014-2019) ACM Nanocom (2016), Hot Interconnects ('10,’16,'17,'19) and external Program Committee for MICRO'12. He has served on multiple NSF panels and several departmental committees. He is the Senior Member of IEEE.
Research Interests: computer architecture, parallel processing, chip multiprocessors (CMPs), network-on-chips (NoCs)
All Degrees Earned: Ph.D., Electrical and Computer Engineering, University of Arizona, 2006; M.S., Electrical and Computer Engineering, University of Arizona, 2003; B.E., Electronics and Communications, Manipal Institute of Technology, Mangalore University, 2000
- Randy Morris, Avinash Kodi and Ahmed Louri, “Reconfiguration of 3D Photonic On-chip Interconnects for Maximizing Performance and Improving Fault Tolerance,” 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45), Vancouver, BC, Canada, Dec 1-5, 2012.
- Randy Morris and Avinash Kodi, “Exploring the Design of 64 & 256-core Power-Efficient Nanophotonic Interconnects,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 16, no. 5, pp. 1386-1393, September/October 2010.
- Dominic DiTomaso, Avinash Kodi, Savas Kaya and David Matolak, “iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture”, 19th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects), Santa Clara, California, August 24-25, 2011.
- Avinash Kodi, Ashwini Sarathy, and Ahmed Louri, “iDEAL: Inter-router Dual-function Energy- and Area-Efficient Link design for Network-on-Chip (NoC) Architecture,” Proceedings of the 35th International Symposium on Computer Architecture (ISCA-35), pp. 241-250, Beijing, China, June 21-25, 2008.
- Avinash Kodi and Ahmed Louri, “Performance Adaptive Power-Aware Reconfigurable Optical Interconnects for HPC Systems,” Proceedings on ACM/IEEE Conference on High-Performance Networking and Computing, SuperComputing (SC’07), Reno, Nevada, November 10-16, 2007.
- NSF CAREER (2011-2016)