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School of Electrical Engineering and Computer ScienceFPGA Lab |
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In this lab we will design a simple 4-bit counter. The design is written in VHDL codes that will be synthesized and implemented using FPGA Express . The resultant xilinx netlist format (xnf) file is then used by the Design Implementation tools to generate the bit stream file (bit). Then the file can be downloaded to the XC4010XL chip. The counter will count continuously from 0 up to F (hex counter) with frequency of 1 Hz and will be displayed in the LED of the board. |
| 1-Create in your directory five empty files
named count.vhd count4.vhd, osc_4k.vhd, clkdiv.vhd and
seg7dec.vhd.
2-Cut the following codes and paste them in the files you created in step 1. File1
: count.vhd
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First Part: FPGA Express: 3-Start the FPGA Express by clicking on the icon in the desktop. 4-Choose create a new project. Then write the project folder name. This should be in your directory. Then Identify the VHDL source files( the five files we have). 5- You will see a green sign to the left of the files. This means that the codes do not have any syntax error. If you did not find those green signs then: From the menu of the toolbar choose synthesis- analyze all. 6- Choose the count.vhd file, and use the right button to create implementation. In the new window, make these options: (the top-level file is count-rtl, vendor = Xilinx, Family = XC4000, device = XC4010XLPC84, speed = -3, and remove the mark near the keep user pads option. 7- You will see the implementation icon and name. Select this implementation. Synthesis- open implementation. Click on ports from the new window. Modify the pad locations as shown here.
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Then save your work. Close the last window. Choose Synthesis-optimize. A new icon and name appears. Select this new icon and then, click FILE- export Netlist and choose your directory location. |
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PART -II Design Implementation Tools: 8- In the desktop, click on the Design Manager (or Design Implementation) icon. Choose FILE-new project. Then in the Input design field, choose your design by browsing to get the netlist file (count.xnf) which is located in your directory. Then click OK. 9- Choose Design-Implement. From the new window choose RUN. 10- After the configuration is done and the bitstream file is generated, download your design using the dos command: xsload count.bit.
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| back to FPGA LAB |