This lab (Lab1) is intended to get you started with the tools in the lab associated with EE690 (Reconfigurable Design). It gives a quick overview of how to create a schematic, simulate it and download it into a FPGA. For more detailed information please consult the on-line XILINX documentation, or the XILINX Programmable Logic Data book. 

1. Design Flow Overview. 
2. The FPGA chip. 
3. Starting a new project: Schematic Entry. 
4. Simulating a design.

 The design flow FPGAs consists of three main steps as is illustrated in Figure 1.1. 

 Figure 1.1: Design flow overview (Ref. Xilinx Programmable Logic Data book). 

The design process consists of (a) Design entry, (b) design implementation and (c) design verification. Designs can be entered in various ways: using a schematic editor to draw a logic diagram, using a hardware description (ABEL or VHDL), or a combination of both. The tools also support hierarchical design entry. 

The implementation tools fit the entered design into the target device architecture. The tools are highly automated and will compile a design file into a configuration file that is optimized in terms of use of logic gates and interconnections for the targeted device. Downloading of the bitstream can be done easily from a PC into a FPGA (in the XS40-010XL board) through a parallel cable connecting the board to the PC. FPGA's can also be programmed in-the-system (ISP) by connecting a XChecker cable to their programming pins. 

Design verification includes functional simulation, in-circuit testing, and timing simulation. Functional simulation can be done after the design entry to verify the proper operation of the circuit. However, functional simulation does not provide timing information, such as delays, race condition, set-up and hold-time violations. This information is obtained from the static timing simulator and is done after the design has been compiled for the target device. 

There is only one type of programmable logic devices we will be working with. It is called a field programmable gate array (FPGA). We will mainly be using the XC4010XL FPGA which belongs to the XC4000 family of FPGAs. The XC4000XL is a low power device with a 3.3V Vcc but with 5V tolerant I/Os. 

The devices come in a variety of packages. The one we are using is packaged in an 84 pin PLCC and have the following part name: XC4010XLPC84. 

You will have to specify this part name when starting a new project so that the tools can optimize the design for the specific device you plan to use. Once you have a design, it is easy to change which component you target your design for as will be discussed in the "Design Implementation section". Detailed information on this device is given in the Xilinx Programmable Logic Data Book. 

Lets assume you want to build a really simple circuit, as shown in Figure 3.1. The corresponding Boolean expression is: F = A.(B' + C') 

Figure 3.1: Schematic diagram used in the example below.

To start the Xilinx Foundation tools (click on the icon or go to the window's START menu - Programs - Foundation set - Foundation Program Manager). The Project Manager window will open as shown in Figure 3.2. This window shows the design flow as well as the associated tools. 

Figure 3.2: Xilinx Foundation Project Manager window (Screen clip from Xilinx XACTstep(TM) Foundation software) 

First create a new project by going to the FILE menu - CREATE NEW PROJECT. This will bring up the new project window: 

Fill out the name of the project, the directory where you want to store the project, and the Type. Lets give it the project Name: Proj1 . The project name is not case sensitive. 

For the type select XACTstep M1. The family refers to the device family, so select XC4000XL. The part refers to the specific device. Check the type of device you have on the board. The XS40-010XL FPGA board will probably be populated with the XC4010XL-PC84, so, select it. The speed refers to the speed specification of the device( you can choose -3). You can change the target device at a later time by clicking on the Design Info icon in the Project Manager window (Fig. 3.2). 

The project will have an .PDF extension. Other project files such as schematics, netlists, macros,etc., will be stored in a subdirectory with the project name. A project can have only one top schematic (or HDL source file). Sub-schematics can be added to the project as macros. 

 b. Schematic Entry 

To create the circuit of Fig. 3.1 using the Schematic editor, click on the Schematic editor icon in the Project Manager window or select the APPLICATIONS menu - SCHEMATIC EDITOR. A Schematic Capture window will appear. 

 i. Placing symbols: 

You can add the logic symbols by clicking on the icon of the NAND gate (Symbols icon) on the toolbar on the left. An SC Symbols window will pop up. You can scroll down the list and select AND2 or type the symbol name at the bottom box of the list. Notice that a brief description of the selected symbol appears at the bottom. You can now place the gate with your cursor on the schematic by clicking the mouse. To place another AND gate just click on the previous one and a second gate will be attached to the cursor. Everytime you click another gate of the same type will be placed in the schematic. Place two 2-input NAND gates. Next, select OR2 from the SC Symbol list and drop one OR gate. 

Be careful not to place the symbols too close together so that they are next to each other as if they are connected. They are not electrically connected. Symbols have to be connected with so make sure you leave some space between the gates to wire them up! The integrity test does not report an error if this happens. You can mirror a symbol by pressing Ctrl+M keys or rotate it by pressing the Ctrl+L keys. To redraw the screen press the F10 function key. 

Note: The FPGA comes with an on-chip oscillator of 8 MHz. This can be used by placing the symbol OSC4 in the schematic (or HDL code). An internal divider makes the following signals available: 8MHz, 500 kHz, 16 kHz, 490 Hz and 15 Hz. 

ii. Adding I/O buffers, pads and I/O terminals: 

FPGAs have input/output blocks that act as an interface between the internal circuitry and the pins which connect to the external world. The I/O block can be configured by the user. It consists of input and output buffers (designated by the library symbols IBUF and OBUF), tri-state output buffer (OBUFT) and flip-flops (edge-trigger D flip flop (IFD) or a latch (ILD)). Output pins are pulled-high through a pull-up resistor of about 10 kOhm when not in use to prevent floating outputs. During normal operation, the pull-up is deactivated. 

Buffers are needed for inputs and output signals which go to a pin of your device (FPGA). Place the buffers on the schematic in a similar fashion as you did for the other symbols. For the input buffers select the IBUF symbol and for the output buffer select OBUF from the SC Symbol list. In case you like to add a tri-state buffer, you can select OBUFT. Do not forget to add buffers or your schematic will not compile later on! 

Pads:You will also need to add I/O pads to the input and output buffers. These pads represent the actual pins on the XILINX device. A pad is a physical component in the Xilinx Unified Library and is placed like any other component (ex. AND, NAND, etc.). The names of pads are IPAD (input), OPAD (for output), IOPAD (bidirectional), IPAD4 and OPAD4, etc. All device pins MUST be represenented with one of these I/O pads! Pads should be given a name and possibly a pin number (pin location). This can be done by double clicking on the pad to bring up the Symbol Properties window (see Adding pin locations below). 

Pins: An I/O terminal (pin), which is available by clicking on the I/O Terminal buton on the left-hand side of the toolbar at the top of the SC Symbols window, is not a physical device and cannot be used as an I/O pad (although, sometimes the software may treat it as an I/O pad, but there is no guarantee). I/O terminals should only be used to provide connection between levels of hierarchy in the design. Thus they are used in macros to connect signals to the corresponding pins on the macro symbol. However, signals that span multiple pages of a flat design do not require terminals or off-page connectors. To indicate device pins on the top-level schematic in a hierarchical design, one should not use I/O terminals but pads to indicate device pins. 

If the schematic is going to become a cell or macro that will be used later on in a larger schematic you need to use I/O terminals to indicate the terminals of the device. As explained above you can add a I/O terminal (pin) by clicking on the Terminal button and entering the name of the terminal. For macros, you don't need to place buffers in the schematic (IBUF or OBUF) since the inputs and outputs will not be connected to a physical pin of the FPGA. For macros or hierarchical design, see the section on "Macros and Hierarchical Schematics". 

iii. Drawing lines and naming wires: 

To connect one gate to the other, use the Draw Wire feature. This can be done by clicking on the wire symbol just below the icon of the NAND gate. All symbols must be connected with wires. Do not put symbols close together in order to leave space for the wire to connect them together. Nets (wires) should be user-defined for readability and documentation purposes. You can name a wire by clicking on the "Wire Icon with A" just below "bus" icon on the vertical toolbar. Type in a name in the Net Name window and put the cursor over the location of the wire. A shortcut to naming nets is double clicking on the net. You can now fill out the netname between the pads and buffers for the three inputs (A, B AND C) and the output (F). Net names should appear in blue (green names indicate that the name is not connected to a net). 

 iv. Adding pin locations: 

You can assign pin numbers to each input and output pin. If you don't do this, the compiler will assign the pin numbers for you. There are two ways you can assign pin numbers. First, you can place the pin numbers on the schematic using the LOC or Description property. This is done by double clicking on the PAD symbol. In the pop-up Symbol Properties window (Fig. 3.5) , go to the Parameters section and enter as Parameter Name: LOC, and for the Parameter Description: P#, in which # represents the pin number as shown in Figure 3.3 (the letter P is required in front of the number). Click on the ADD button. To display the pin location, double click on the LOC=P19 till two diamonds appear next to it. When finished click OK. 

The name can be moved by double clicking on the pad till the Symbol Properties window appears. Select LOC=P# and select MOVE. You can now move the pin location label around. 

Figure 3.3: Symbol Properties window to assign pin locations (Screen clip from Xilinx XACTstep(TM) software window) 

An alternative way is to not assign pins on the schematic, but specify the pin numbers later, before compiling the design. This can done by creating a User Constraint File. The advantage of the latter method is that the schematic is more generic and you can easily change pins without having to modify the schematic (or ABEL HDL code). Figure 3.4 shows the finished schematic. 

When using the Demoboard, the XS40, certain pins have been pre-assigned and some are connected to LEDs and switches for ease of testing (consult the descriptions of the XS40 board). Assign the pin numbers so that you can make use of these devices. 

Figure 3.4: Schematic of the finished circuit including pin numbers locations (Screen clip from Xilinx XACTstep(TM) Foundation software) 

v. Save your schematic 

Go to the FILE menu - SAVE AS or click the floppy disk icon on the top toolbar. Give your schematic a name with the extension .SCH (ex. EASYPROJ.sch). When finished with the schematic, exit the Schematic capture program which will bring you back to the Foundation Project Manager window (Fig. 3.2). 

vi. Adding the schematic to the project 

If the created schematic is not listed in the Project Manager window under the Project you created (ex. Proj1) you have to go to the DOCUMENT menu - ADD in the Project Manager window. A window with a list of files will appear. To show only the type "Schematic" display *.SCH in the dialog window. Then select the schematic (PROJ1.sch) you would like to add to your project (Proj1). 

4. Simulating a circuit (Functional Simulation):

At this point we can do a functional simulation to verify that the circuit works properly. Click on the "SIM Funct" icon in the Project Manager window (Fig. 3.2). The current version of the design will be loaded. The Foundation Logic Simulator window will pop up with a Waveform Viewer window. 

To simulate the circuit you do the same as if you were testing the circuit in the lab: add input signals to the input pins and view the input and output waveforms. Thus the first step is to specify the input signals. This is done by clicking on the CHIP icon on top of the Waveform Viewer window or by going to the SIGNAL menu ->ADD SIGNAL. Now another window will appear, called the Component selection window, as shown in Figure 4.1. 
 

Figure 4.1: Logic Simulator window with Waveform viewer and Component Selection windows (Screen clip from Xilinx XACTstep(TM) Foundation software) 

In the Component Selection window, select the inputs you want to add to the waveform viewer and click the "Add" button. Do this for all inputs and outputs. These signals will appear in the Waveform Viewer window. 

You can also select test pins by going back to the schematics and add probes to the wires you would like to test by clicking on the test probe icon. 
 

Next you need to add a stimulus to the input signals. 

• This is done by clicking on the Stimulator icon (on the top tool bar - the icon with the two square waves) or by going to the STIMULATOR -> ADD STIMULATORS menu.
• A new window will appear which looks pretty complicated, shown in Figur 4.2. The stimuli are digital signals. One convenient way is to specify them as outputs of a clock generator (binary counter) which cycles through all binary possible combinations.
• This can be done by using the 16-bit binary counter, labeled "Bc" on the Stimulator Selection window. This is a 16-bit counter whose first four outputs are labeled from B0 to B3; the next four bits are labeled B4 to B7, etc. The outputs will go through the following sequence: 0000 0000 0000 0000 > 0000 0000 0000 0001 > 0000 0000 0000 0010 .... > FFFF FFFF FFFF FFFF > 0000 0000 0000 0000. The clock period of the B0 output is 10 nsec, the next output B2 has period of 20 nsec, etc.

Figure 4.2: Stimulator window and Simulation window (Screen clip from Xilinx XACTstep(TM) Foundation software) 

In our case we need to use only three outputs of the counter. We will use the lower three bits. Click on the signal name in the Waveform viewer first (Ex. DOOR) so that it is highlighted, then click on the most left side counter output (labeled 0). The name B0 will appear after the signal name in the Waveform Viewer. Do the same for the other three input signals (select the next two counter outputs). 

You can also assign a keyboard key to the signal, to manually toggle the signal. This is done by selecting one of the keys on the Keyboard section in the Stimulator window. For more information, click the HELP button. When done, close the Simulator Selection window. 
 

At this point we can do a functional simulation. In the small Simulator window (somewhere on the top right corner of the screen) click the Mode button and select FN (functional simulation). Next, click on the LONG or STEP buttons to initiate the simulation. The inputs and corresponding output waveform are displayed, as shown in Figure 4.2. You can change the scale of the time axis by clicking on the ruler icon on top of the Signal list. The time scale is displayed as well. 

You can switch back to the schematics window by clicking on the SC icon in the Simulator window. The schematic window will show the actual logic levels (0 or 1) of each of the signals added to the Waveform Viewer window. In the SC Probes window you can click on the STEP icon to step through the simulation. The results will be shown on the schematic for the signals you have added to the Waveform Viewer window. You can add additional signals by clicking on the Probe icon in the SC Probes window. Click on the nets that you like to display. 

Now you can verify if the circuit performs as expected. If problems occur, check your logic or the schematic. A common problem is symbols which are not connected together with wires because they were placed too close together. You cannot tell easily from the schematic. 

Notice that the functional simulation tells you only about the logic but not about timing. This means that no information about gate delays (and thus max. frequency), hazards or set-up and hold-time violations can be extracted from the functional simulation. Once you have compiled your design for a specific device, you can do the timing analysis. 

v. Displaying signals as buses 
 

If you have many signals to display, it may be more convenient to group them into a "Bus". This can be done by first selecting the signals you like to group and then going to the SIGNAL -> BUS -> COMBINE menu. The value of the signals of the bus are displayed in HEX notations (unless otherwise specified). You can also flatten a bus by going to the SIGNAL -> BUS ->FLATTEN menu. An example of a simulation with buses is shown in Fig. 4.3. 

Figure 4.2: Waveform Viewer window in which the signals have been combined into buses (Screen clop from Xilinx XACT(TM) Foundation software)