--      
-- FREQ. DIVIDER input of 15Hz output of 1Hz 
-- 

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity clkdiv is
	port (I: in std_logic;
	      O: out std_logic);
end clkdiv; 

architecture rtl of clkdiv is
signal QOUT: std_logic_vector(3 downto 0);
begin
    process (I) 
	begin
	if (I'event and I='1') then
	    QOUT <= QOUT + 1;
        end if;
   end process;
O <= QOUT(3);
end rtl;