Modified by Lily Li
In contemporary design flows, test merges with design much earlier in the process, creating what is called a design-for-test (DFT) process flow. To ensure maximum design testability, designers must employ special DFT techniques at specific stages in the development process. Figure 1 shows the basic steps and the Mentor Graphics tools you would use during a typical ASIC top-down design flow with a structured DFT strategy. As those steps shown in grey indicate, if your design's format is in VHDL, you can use BISTArchitect to synthesize BIST structures into its memory and random logic design blocks. Also at the RTL-level, you can insert and verify boundary scan circuitry using BSDArchitect (BSDA). After you synthesize and optimize the design, you are ready to insert internal scan circuitry into your design using DFTAdvisor. When you are sure the design is functioning as desired, you can use FastScan or FlexTest (depending on your scan strategy) to generate a test pattern set via ATPG methods. Before handing the design off for manufacture and testing, you should verify that the design and patterns still function correctly with the proper timing information applied.
For details about DFT concepts, refer to the .pdf version document ASIC/IC Design-for-Test Process Guide using mgcdocs command.
This lab will cover:
1. Using DFT Advisor to insert full scan.
2. Using Fastscan to generate test vectors and test fault coverage.
DFTAdvisor is a utility that allows you to insert scan circuitry into your design. It follows one of two basic strategies: The first is full scan. Full scan converts every flip flop and latch into scanable flip flops, which allows the use of combinational test pattern generation. After inserting the scan circuitry, you can then generate test vectors for your design by using Fast Scan. The other strategy is partial scan. With partial scan you only insert scan circuitry in some of the memory devices.You can then generate test vectors for your design using FlexTest.In this lab exercise, you will invoke DFTAdvisor on a simple design to insert full scan. You will use DFTAdvisor to write a scan-based netlist file and ATPG setup files. Then you will invoke FastScan using the ATPG setup file information to create, compress, and save patterns. This lab will give you experience using the tools in a typical scan and ATPG tool flow utilizing default configurations.
This Verilog design contains no errors, so you can use it as a future reference to help you navigate through a scan and ATPG tool flow.
Understanding and applying these concepts will assist you when you begin to make customized configurations to enhance tool performance.
1. DFT Advisor requires a test library. A test library gives the functions of all the gates in the design and how to convert the non-scannable flip flops into their scannable equivalents. Please download the library adk.atpg. Make sure to save this file in the current working directory.
2. Put your HDL file in the current working directory. The source codes are in section 4. Please download the pipe_net_noscan. Make sure to save this file in the current working directory.
This invokes the DFTAdvisor Invocation Arguments dialog box. You must enter a design, a design format, and an ATPG library to invoke the Graphical User Interface (GUI) as shown in fig. 2.
a. Click the Browse button next to the Design field to enter the design. Click the pipe_net_noscan.v design. Notice the design path is inserted into the Design field. Click the OK button in the dialog box.
b. Select the Verilog design format from the Format dropdown list, if not already selected.
c. Click the Browse button next to the ATPG Library field.
i. Navigate to the libraries directory.
ii. Select the adk.atpg library file.
iii. Click OK.
d. Click the Browse button next to the Log File field, then navigate to the your desired directory where you can save your results. Back over the .*. in the File Name Field, and type dftadvisor.log into the command path. This will create a log file that logs all of your session, including reading in the library and the non-scan netlist at invocation.
e. Click Ok. The File Browser closes.
f. Click Invoke DFTAdvisor. DFTAdvisor is now up and running. You have successfully invoked DFTAdvisor on the pipe_net_noscan.v design. Both the Command Line and the Control Panel windows should now be open.
Define clocks. Clocks are primary input signals that asynchronously change the state of sequential logic elements: clocks, sets, resets, and RAM read/write clocks.
a. Choose Setup > Clocks menu item. Or click on the Clocks button in the Circuit Setup graphics pane, a Setup Circuit Clocks dialog box open as shown in fig. 4.
i. Click on the Automatically Identify & Add button.
ii. Click on the Apply button. The /clk control signal is identified and the Off-State is 0.
iii. Click OK.
Alternatively, you can use the Analyze Control Signals -Auto_fix command to automatically identify clocks and control signals.
Besides defining scan circuitry, defining (or adding) clocks and pin constraints is the key to successful Design Rules Checking (DRC).
These are the most critical steps; you must load scan patterns correctly and you must clock circuitry at the proper time to ensure correct fault simulation.
3. Go to DFT mode.
a. Click Done with Setup in the DFTAdvisor control panel pane. You are now in the DFT system mode.
When you switch from SETUP to DFT mode, DFTAdvisor and FastScan will run DRC.
DFT mode is primarily for scan identification and insertion.
The Test Synthesis window is displayed in the graphic pane. Also, Test Synthesis is highlighted in the task flow manager pane.
Note: If DFTAdvisor encounters DRC violations that are errors, it will not exit SETUP mode. You must debug and fix the problem in SETUP mode before proceeding. If no error encountered, then an interface as shown in fig. 5 will show up.
4. Choose full scan methodology.
Click Setup Identification button in the graphic pane. The Setup for Scan &
Test Point Identification dialog box opens as shown in fig. 6. The Full Scan button is selected (red), which is the default setting. Full scan methodology is the fastest identification method.
a. Click OK.
5. Identify scannable instances.
a. Click Run Identification in the graphic pane.
b. Observe the default settings.
c. Click the Run with Existing Settings button. The DFTAdvisor Identification Run Statistics box opens.
i. Observe the information that is available.
ii. Click the View Details button. The Scan Identification box opens.
iii. Click the Close button for this dialog box.
iv. Click the Report button. The Results & Analysis box opens.
v. Click Show Statistics.
vi. Click Generate Report.
What information is displayed?
vii. Click Close.
ix. Click Dismiss. This closes the DFTAdvisor Identification Run Statistics dialog box.
d. Click Setup/Run Test Synthesis in the graphic pane. This opens the Setup/Run Test Synthesis box as shown in fig. 7.
e. The following default settings should be selected (red is active)
Synthesize Scan Circuitry into the Design
Synthesize Identified Test Points
Synthesize Test Logic to Control RAMs
f. Click Setup in the Synthesize Scan Circuitry into the Design area.
i. In the Chain Restrictions area, the insert button is selected (red), and the number 1 is entered in the Chain entry box.
ii. In the Scan Enables area, the Allow Only One Scan Enable Signal to
Control All Scan Chains is selected (red).
g. Click Done.
DFTAdvisor can automatically insert a number of different test structures into the design. These structures include: scan circuitry, test points, test logic to RAMs, I/O buffers for added test pins, and buffer trees for test pins.
h. Click OK. A box as shown in fig. 8 will pop up.
i. Click Run with Existing Settings. You just inserted full scan into the design using the default settings.
A scan-inserted netlist has now been created.
6. Save a Verilog netlist and ATPG setup files.
a. Click the Save Results button in the button pane. This opens the Save Results dialog box shown in fig. 9.
b. Click Save the New Netlist button.
c. Select the Verilog format from the Format dropdown list, if not already selected.
d. Click the Browse button next to Pathname in the Netlist area.
i. Navigate to the results directory. Save as pipe_scan.v file.
ii. Click OK.
iii. Click the Overwrite Existing File button. This automatically overwrites the existing file with each save.
e. Click Save Setup Files for ATPG button shown in fig. 10.
f. Click the Enhanced Procedure File button (red when active) in the Timing File Type area. The Enhances Procedure file describes the order of events for a test pattern set and introduces timing to test vectors divided into cycles.
g. Click the Browse button next to Basename in the Setup for Test Points area.
i. Navigate to the results directory. Save as pipe_scan (without a file extension).
ii. Click OK.
h. Click the Overwrite Existing File(s) button.
i. Click the View Files button. This activates the File Viewer when you have saved the output files.
j. Click OK. This closes the Save Results dialog box.
You have written the following three files:
pipe_scan.v, which is the Verilog netlist
pipe_scan.dofile, which is a dofile file
pipe_scan.testproc, which is an Enhanced Procedure file
k. The File Viewer is now open.
i. The pipe_scan.dofile is displayed as shown in fig. 11. This file inputs circuit setup and scan information needed by FastScan at invocation.
ii. Double-click the pipe_scan.testproc in the Select File to View display area. This displays the shift and load_unload procedures as shown in fig. 12, as well as the timing plate (gen-tp1), which is shared by both procedures.
l. Close the Viewer.
For this exercise, you will invoke FastScan from DFTAdvisor. The goal for this part of the exercise is to follow a typical ATPG tool flow.You will use FastScan to create, compress, and save patterns following the FastScan tool flow
4. Invoking Fastscan
1. Run FastScan.
a. Click Done with Test Synthesis button in the graphic pane.
The DFT Advisor Test Synthesis Complete dialog box opens. Click Run ATPG button. The Exit DFT Advisor before starting FastScan question box opens.
i. Click No.
FastScan is now up and running. You have successfully invoked FastScan on the pipe_scan.v design. Both the Command Line and the Control Panel windows are open as shown in fig. 13. The Circuit Setup graphic pane opens, and Setup is highlighted in the Process Pane.
FastScan completed the following:
Compiled the library
Read in the Verilog Netlist
Read in the Verilog file (pipe_scan.v)
Read in the test procedure file (pipe_scan.testproc)
Read in the dofile (pipe_scan.dofile)
This is displayed in the session transcript area.
2. Go to ATPG.
a. Click Done with Setup in the Circuit Setup graphic pane. The FastScan Session Purpose dialog box opens as shown in fig. 14.
b. Click the Pattern Generation button. The Test Pattern Generation graphic pane opens. Also, Pattern Generation is highlighted in the process pane.The following processes occurred:
Design hierarchy is reduced down to its simulation primitives and connectivity.
Analysis by FastScan to learn circuit behavior, used later in fault simulation and ATPG.
FastScan performs static learning only once after flattening. Static learning involves gate-by-gate local simulation to determine information about the design. Pin and ATPG constraints are not considered.
Design Rules Checking (DRC)
The tool exited SETUP mode and entered the ATPG mode. This is displayed in the session transcript area.
3. Select fault model and add faults.
a. Click on Fault Universe in the Test Pattern Generation graphic pane.
b. Click the Typical button.
The Stuck-at-Fault model is chosen, which adds all faults into the design.
4. Generate patterns.
a. Click on Test Generation in the Test Pattern Generation graphic pane.
Use Existing Settings or Customize? dialog box opens.
b. Click Run with Existing Settings. ATPG Run Statistics window comes up as shown in Figure 15, click on Dismiss.
You just generated test patterns following a typical ATPG flow process.
The following information is available:
Number of Effective Patterns
Number of Simulated Patterns
Number of detected
Number of aborted (untestable)
Number of ATPG Untestable (AU)
Number of undetected--uncontrollable (UC) or unobservable faults (UO)
Test Coverage percentage--percentage of all testable faults that are detected by the pattern set
Fault Coverage percentage--percentage of all faults both testable and untestable that are detected by the pattern set
ATPG effectiveness percentage--a measure of the ability of the ATPG tool to either provide a test to detect a fault, or prove that a test cannot be created
CPU run time
c. In the right side of control panel, click on Save Pattern, select Save the Pattern Set to a File, specify the pathname, select ASCII format, and click OK.
5. Results and Analysis
a. From the Test Pattern Generation click on Results and Analysis, select Report Faults on All These Design Objects and Both of the Above (SA1 and SA0), and click on Show Statistics.
b. Report Statistics comes up, click on Entire Design option. Then the Statistics report will be shown. Click Close to close Results & Analysis.
c. We are done with ATPG. Next step is Fault Simulation used the same pattern that just generated by ATPG. In Test Pattern Generation panel, click on Done With Pattern Generation, and click on Fault.
a. In Fault Simulation control panel, click on Pattern Source. Setup Pattern Source comes up, select External Patterns From, navigate to the same pattern file and same format generated by ATPG, and click OK.
b. In the right side of Fault Simulation control panel, click on Run button. FastScan Fault Simulation Run Statistics will be shown, and click on Dismiss.
c. Results & Analysis
From the Fault Simulation click on Results and Analysis, select Report Faults on All These Design Objects and Both of the Above (SA1 and SA0), and click on Show Statistics.
Report Statistics comes up, click on Entire Design option. Then the Statistics report will be shown.