Author: Richard K Wallace
Date: 7/28/99

How to Size the Transistors in a Complementary Static CMOS Device

Introduction: To equalize the response time in the in the pull up and pull down networks of a device, transistor sizing is necessary. Transistor sizing involves increasing the gate width to increase its speed (Figure 1).

Figure 1: Physical Transistor Model

All Combinational Static CMOS devices are composed of Pull up networks and Pull down networks. The response time for the Pull up networks is called TpLH (Time Low to High) and the response time for the Pull down network is called TpHL (Time High to Low). These times are in reference to a Load Capacitor charging and discharging through the device. When the Pull up network is active the Capacitor gains charge from VDD. When the Pull down network is active the Load Capacitor discharges into VSS (Figure 2).

Figure 2: Pull up and Pull down networks

The pull up and pull down networks are composed of transistors that are either in series or parallel combination. A switch and a series resistance (Figure 3) can model these transistors.

Figure 3: Transistor Model

Transistor sizing is the process of evaluating different paths through both the Pull up and Pull down network. These paths and the resulting composite resistance of that path will determine each transistor width in the path (Figure 4).

Figure 4: Pull Down Path Example

Consider the Pull down network of Figure 4. If the transistors were sized identical then the left hand path would require twice as long to discharge the load capacitance than the path of the right hand side. The solution to the problem is to double the width of the transistors on the path of Ra and Rb, which would make them twice as fast as the transistor on the path of Rc (Figure 5).

Figure 5: Sized NMOS

Sizing of the Pull up network is done in the identical manner as the pull down network with the further exception that PMOS devices must be scaled 3 times wider than NMOS devices to compensate for their reduced mobility (E.g.: pushing protons across the device is harder than pushing electrons). Figure 6 displays the final circuit sized correctly.

Figure 6: Final Circuit

For the Pull up network of Figure 6 the left and right hand path from VDD to CL has two transistors. Therefore, both paths in the Pull up device will take twice as long as the singular transistor path in the Pull down network. The solution is double the width of every PMOS transistor and then triple their widths to account for the compensation factor (minimum width x 6).

Reference: Chapter 4, section 4.2, Digital Integrated Circuits, Jan M. Rabaey