Lab 3: Simple Sequential Circuit (State Machine)



1. Objectives:


This lab will implement a stopwatch mainly based on a finite state machine (FSM). Other parts contain display, timer, counter, etc. The main aim is to make you understand the sequential circuit (state machine) to be used in our more complex system in the future. In detail, the lab will implement:


a. Design a simple timer that counts in 1/100th of a second increments. This can be done by feeding the timer with a 100Hz clock. It should be possible to start and stop the timer on demand by using a single start/stop inputs which are the switches on the Spartan 3 board.

b. The enable, reset and run outputs are used to control the display on the seven segment LED. These control inputs are also the push-buttons on the
Spartan 3 board.

c. Each digit of the timer will have a 4-bit output. When the 1/100 th of a second digit (digit 0) counts up to 9, the 1/10th of a second digit must increment its count by one. In addition, the 10s of seconds digit (digit 3) must reset to 0 after the timer has counted 59 seconds.


2. Background Information:


Until now, we mainly deal with combinational circuits including its design and timing analysis. In this lab, we will build a sequential circuit a stopwatch state machine. The concept of a state machine (or sequential circuit -- the terms will be used interchangeably) was introduced during the class -- it will be explored more thoroughly in this exercise. When the solution to a problem requires that a circuit implement a specific sequence of events, a sequential circuit is required. For example, when transient inputs (such as a user pressing buttons) must direct the algorithmic flow in a given situation, a state machine is needed. A combination-lock door controller, where numbered buttons must be pressed and released in a prescribed order, provides an example of such a situation. In this application, a state machine is required to detect a valid sequence of button presses. This is entirely different than problems for which a circuit can simply combine all the inputs present at a given time. For example, a circuit to detect when the CTRL-ALT-DEL keyboard keys are simultaneously pressed requires no sequential behavior -- the output can be generated by a simple logic gate. As you already know, circuits that do not require memory to perform their functions are called combinational circuits (as distinguished from sequential circuits). In some cases, machine states appropriate for given problems are readily defined (in the first example above, each new button press requires a new state), but in the general case, the most difficult design challenge lies in choosing proper machine states. Recall that a state machine is a circuit that possesses one or more memory devices, and that the collective contents of all memory devices define a machine's "present state" at any given time. The value stored in each memory device in a state machine is referred to as a "state variable". Since a state variable can only take one of two values (logic 1 or logic 0), a circuit with N state variables must be in one of 2N states. All memory devices in a given state machine are collectively referred to as the state register (a register is simply a collection of one or more memory devices that all share the same clock signal, and so are all written in parallel). Since a D-FF can always be used to implement a minimal circuit for any state machine, the use of D-FF's in state machines will be assumed for the remainder of the lab course. So a state machine with N state variables requires N D-FF's and has 2N possible states, where each state can be identified by the N-bit binary number formed by the state variables.



Note that the state register holds all the memory devices, and that the next-state circuit only contains combinational logic. Inputs to the next-state combinational logic circuit come from two sources --feed-back from the present state variables, and inputs from the outside world (for example, inputs may come from user-accessed buttons or switches). Note that without present-state feedback, a state machine could not perform a given sequence of actions. Any combinational logic circuit can be completely defined by a truth table, and a next-state logic circuit is no exception. A next-state truth table would require N input columns for each of N present-state variables, and M input columns for each of M circuit inputs. It is not required that all possible states nor all possible combinations of inputs be used; hence, the next-state truth table need not have all 2(N+M) rows present. Just which rows are required in the truth table depends on which of the 2N possible states are used in a given sequential circuit, as well as which inputs are used in each state (we will spend much time in deciding how many state variables and how many states are required for a given problem). For each row of the truth table, the output values are assigned according to the desired next state. Since we are assuming D-FF's, a '1' in an output column will cause the corresponding D-FF to transition to a '1' on the next clock edge. Thus, the truth table has inputs and present state codes on the "input" side, and next state codes on the "output" side. When a truth table is used to define the next state logic, it is often referred to as a state table. Although a state table can always be used to specify next-state logic, a more useful method exists. This method, that of defining circuit behavior by using a state diagram, has the added advantage of providing a powerful conceptual tool for describing the algorithmic behavior of a circuit. In use, a state diagram represents states with open circles, and transitions between states by arrows exiting one circle and arriving at another. When a state diagram is used as a conceptual tool to help arrive at a given problem solution, it is typically sketched and modified in an iterative fashion. Circles are drawn representing possible states, interconnected according to problem requirements, and redrawn and reconnected as the problem and solution become more clear in the designer's mind. An example of a simple state machine is shown below. This machine receives input from three buttons labeled X,Y, and Z, and asserts a signal called "RED" only if the three-button-press sequence X-Z-Y is detected. Note that transition arrows from each state are annotated with the input conditions that cause the transition, and that output assertions are shown adjacent to each state. (Some state diagrams make use of the "Xbar" notation for X='0' -- this should cause no confusion).


Once the sequential behavior of a problem has been captured with a state diagram, state variable values (in the form of binary numbers) can be assigned to each state. Keep in mind that these state variable values represent the actual contents of the state register when the state machine is in that state. The state variable values assigned to each state are known as the "state code". The state code is typically written inside state diagram circles to uniquely associate each state with a particular binary number that will be stored in the state register when the state machine is in that state. For a state diagram with N states, at least log2N state variables are required so that each state can be assigned a unique number. In the example above, the state diagram has 4 states, so log24=2 state variables are required. Although any state code can be assigned to any state, in practice certain rules are used to choose state codes. These rules will be examined in a later lab. Once a state diagram has been annotated with state codes and transition requirements, it contains all information required for the design of an optimal next-state logic circuit. Thus, the annotated state diagram contains exactly the same information as the state table (or next-state truth table). The information contained in either a state diagram or state table can be transferred directly to K-maps so that a minimal next state logic circuit can be found. The rules for transferring information from a truth table to a K-map are easily learned and easily practiced -- with experience, the rules for transferring information from a state diagram to a K-map are just as easy. Since the example state machine has two state variables, two K-maps are required -- one for determining each next-state logic circuit (see the state machine circuit schematic on the following page). The logic expressions obtained from the K-maps will result in circuits that will drive the D inputs of the state-variable D-FF's. Note that in the K-maps below, the output of the state variable D-FF's

(called A and B) which define the present state in the state diagram appear as index variables on the K-maps. And note that the circuit inputs (which indicate transition conditions) appear as entered variables in the K-maps. With this convention, when the next state equations are looped from the K-maps, they will be in terms of present state variables and inputs.


The state variable flip-flops, their respective outputs, and the next state logic circuits have been labeled on the state machine schematic so that you can compare the signals in the circuit with the variables in the state diagram and in the K-maps.




(Reference: EE324 webpageat


3. Lab Experience:


In this part, we will implement the stopwatch and download it to the board. Here, system block diagram is provided, the main controller state diagram is also provided. You need to look at them, especially the controller state diagram. Then download the all vhdl files to your directory.


 Block Diagram





State Machine Controller


The state machine diagram of the stopwatch controller is shown below. It comprises fourteen states, out of which only six are stable. The remaining states are transitional states that must be included to ensure that the machine does not switch states when a button is continually pressed (logic '0') for several clock transitions.


State Diagram of Stopwatch Controller


The controller has three main sections. The first section is made up of the four outer states that control the stopwatch operation in regular mode. When the button S is pressed, the machine will cycle between these four outer states, starting and stopping the timer. If the timer is stopped and the L button is pressed, the machine will go to its second section, which will reset the timer. The machine will remain in this reset state until the S button is pressed again to start the timer. If the timer is running and the L button is pressed, the machine goes to its third section, which deals with all lap mode operations. This third section is made up of the eight inner states in the diagram. Two of these eight states begin with "R_". These states are transitional states that are used to "return" the machine to the regular mode. The remaining six states have names starting with "L" to signify that these are lap mode states. While the machine is in lap mode, the latch enable pin of the timer is set high, so that the last value of the counter is continuously displayed on the display unit. The timer can be stopped and restarted while still in lap mode. The four states in the center achieve this function. Examine the stopwatch function of your wristwatch and compare its operation to the state machine above.



Stop Watch VHDL Code

Top-Level description including IO bus interface and stopwatch design. Read the push button A B E D 0 as the control signal L(ap), S(tart), Run, Reset, En,
---Stopwatch top-Level structural description

3. TIMER.vhd      --- 1/100th Sec, 1/10th Sec, 1 sec and 10 sec timer
CLKDIV2.vhd   ---Divide the 36MHz system clock to 100Hz

5.SWFSM.vhd      ---Controller



3.1 Simulate SWFSM.vhd following the given state diagram using the simulation technique provided in Lab1. You should simulate as many states as possible. Recommend to set clock signal 100MHz and simulate step 20ns. ( Need to be done at Stocker Rm. 308)




Now save your simulation waveform to your disk and close this software. You can open and print the wave file in the public lab because the software you use here is accessible from public PC lab in Stocker. Your lab report should contain this simulation waveform.


3.2 Implement your design using FPGA (Field Programmable Gate Array) ( Need to be done at Stocker Rm. 306)


a. Put all the vhdl files from C:\EE224\Lab3 into a new project inside XILINX ISE 5.1i Software (Refer to Lab1 is necessary). Plus you need to download the ucf file from C:\EE224\Lab3 and add it into your project with association to the top design.

b. Follow the direction in Lab1 to synthesize, implement, and create programming file. Remember to assign JTAB clock during the last step (Create programming file).


c. Download your design and ask TA to check the result.




4. Lab Report Guidelines:


In your report (due next week at the beginning of lab) make sure to include simulation waveform and your own state machine (Similarly to the given state diagram. But it is manually drawn from your own simulation waveform. For instance, if you only simulate three states, then in your state machine, you only need to draw three states and connect them correspondingly. It is useless to print out the existing whole state transfer diagram). Plus, you need give out one or two paragraphs of description including your discussion. Limit your report to be within three pagers (Font 12, time new roman and single space).



Requirement Summary:


At the end of this lab session:


1.      Show your TA your design works

At the beginning of next lab session:


1. Submit your report to TA. The report is limited to three pages. A professional science and engineering report should contain precise procedures and conclusions. It contains:

A. Lab discussion;

B. Simulation waveform for the sequential circuit (state machine).

C. Your own state transfer diagram based on B (Section 3 shows the State Diagram of Stopwatch Controller, but you have to draw your own state transfer diagram based on your simulation waveform.


Note: (Remember during the lab, you are recommended to save you simulation waveform to your disk for printing at later time. This will save your time)



Frequently Asked Questions

1. When I simulate the VHDL code, I get some unsigned signal values in my waveform, should I assign initial values for some signals?

Answer: When you download your design on the board, the unsigned signals will use 0 as their default value. But when you try to simulate them on Active VHDL, you can assign some initial values just to verify the functionality.

2. What's the usage of constraint file listed on our Lab page?

Answer: They list all connections to the individual buses and SRAM chip and define the pin locations used for the prototype board. The pins which are connected to the data I/O lines can be used as inputs and outputs for your design. But the pin number (i.e. LOC=P60) is fixed, you can attach it to the corresponding input or output name in your design through the ucf (user constrain file).