Lab 1: 4-bit shift register using Xilinx ISE and FPGA

-by: Yinyin Liu



A shift register is a storage circuit where data is input serially from one end or in parallel and emerges from the other end after a specified number of clock cycles. In this lab, a 4-bit shift register will be implemented in a top-down schematic-based design using synthesis tool Xilinx ISE. By using the sample design - 4-bit shift register, a basic design flow of the Xilinx ISE will be followed, and then the generated bit file will be downloaded to FPGA chip for testing.




1. Shift register


In digital logic circuit, a one-bit shift register can be built using J-K flip-flop or D flip-flop. “D” is the input data, clock is the enable signal of J-K or D flip-flop. After one clock cycle, the value of D is shifted out as output Q. Other signals can be used to enhance basic operation of the shift register. They are “reset” and “preset” signal and “p” as presetted value. This digital logic can be easily implemented in VHDL (very high-speed integrated circuit hardware description language) code and created as a component symbol.


To build up shift register with multiple bits, designers can simply cascade the existing components, as shown below:


The design files will be synthesized in Xilinx ISE tool, downloaded to FPGA chip, and the resulting circuit can be verified through I/O devices.


2. Xilinx ISE toolset


Xilinx XST is a complete FPGA logic-synthesis and optimization tool.  It is a powerful and flexible integrated design environment that allows designing Xilinx FPGA and CPLD devices from start to finish. The Xilinx ISE toolset includes schematic capture, simulation, implementation, and device programming tools. All of these tools can be started from the Project Navigator tool:

The navigator provides a user interface that organizes all files and processes associated with a given design project. It is divided into four main panels as shown.

The sources panel shows all source files associated with a design.

The processes panel shows all processes that are available for a given source file (different source files have different process options). Double-clicking on any process name will cause that process to run.

The console panel shows process status, including all warnings and errors that result from running a given process on a given source file.

The HDL editor panel shows the code for any selected HDL source file. The project navigator will also open other windows as needed for some applications, for example, the schematic capture tool.




3. Prototype system


The prototype system in the lab is Digilent Spartan-3 System Board. The Spartan-3 Starter board provides a powerful, self-contained development platform for designs targeting the new Spartan-3 FPGA from Xilinx. It features a 200K gate Spartan-3, on-board I/O devices. The board also contains a Platform Flash JTAG-programmable ROM, so designs can easily be made non-volatile. The boards also includes several output display devices and several input devices, including a modular 4-digit, 7-segment LED display, 8-leds, a 4-button keypad and 8 switches.


The design files will be synthesized in Xilinx ISE tool and downloaded to FPGA chip, and the result can be verified through these input and output devices.


System Board Spartan-3




1.    Overview of the sample design implemented on the prototype boards


The sample design implements a 4-bit shift register with parallel load on the prototype boards. The registers can be reset by pushing button “Btn0” on I/O board. Switch7 represents the value of input bit “D”. Switch3-Switch0 store the values of “P4P3P2P1” to be loaded. The data loading is performed when button “Btn1” is pressed. Use button “Btn2” to clock the shifting.


The whole design can be divided into three functional modules:  the 4-bit shift register built by cascading one-bit register component (“One_shifreg.vhd”), a small controller controlling the state of reset, load or shift (“Shiftreg_fsm.vhd”), and the I/O interface (“Shiftreg_s3.vhd”). Source codes of these design units are listed as:






To implement the design, the procedure listed below is followed:

(1)  Using existing design of one-bit register (One_shiftreg.vhd) to create 4-bit shift register using schematic editor

(2)  Add other source files (Shiftreg_fsm.vhd, Shiftreg_final.vhd, Shiftreg_s3.vhd) into the design

(3)  Add the pin assignment file (Shiftreg.ucf)

(4)  Synthesize the design

(5)  Generate bit programming file

(6)  Download the bit file to FPGA chip

(7)  Test the design


2. Using existing design of one-bit register to create 4-bit shift register in schematic editor

 (1) Starting Xilinx project navigator and creating a new project. Double click the project manager, and then click File New Project. When the Create New Project window is displayed, input the project location and the project name as shown in the displayed window. Choose the correct values for Device Family, Device, Package, Speed Grade, and Design Flow items respectively. The FPGA chip on Spartan-3 board contains the device that belongs to “Spartan3” family with name “xc3s200”, and includes the package “ft256” with the speed grade is “-4”. Since in the sample design, the top-level file is VHDL code, the design flow is specified as XST VHDL. At last click OK button. Your window should look as shown in the following figure.



(2) Adding source files into the project. Right-click the name of the project > add copy of source. Go to C:\EE102\, add four source files into the project, including “Shiftreg_s3.vhd”, “Shiftreg_final.vhd”, “Shiftreg_fsm.vhd” and “One_shiftreg.vhd”. The one-bit register is already implemented by VHDL code, “One_shiftreg.vhd”. After files are added into the project, double-click the VHDL file in the “sources in project” window, the code will be shown in the HDL editor window.




(3) Creating one-bit register symbol using VHDL code. Highlight the “one_shiftreg.vhd” file, double-click “create schematic symbol” in the process for current source window, a symbol for one-bit register will be generated. Once we open the schematic editor later on, we will be able to see it.



(4) Building 4-bit shift register in schematic editor. The desired design of 4-bit shift register can be built by cascading four of the one-bit register components, just like what we would do on digital circuit prototype. In Xilinx toolset, the cascading procedure can be done by building a 4-bit shift register in schematic editor. Right-click the name of the project>new source>schematic. And name the file name as: “shiftreg_4”.





The schematic editor is opened in a separate window, with a blank palette to which symbols, shapes and lines can be added.


(5) Building 4-bit shift register schematic. The generated symbol of one-bit register (“One_shiftreg”) is available in the list on the left of the schematic editor, when you choose the “C:/EE102/ lab”, the project name in the “categories”. The generated symbols and components in the menu can be drag-and-dropped onto the schematic and then connected by “wire”. Firstly, add 4 of the one-bit shift register symbols in order to make the 4-bit shift register.

Using “wire” in the schematic editor to connect the four shift registers.



Add I/O ports in the schematic. The input ports include “clock”, “reset”, “preset”, “P1~P4” as preset values, “D” as shift-in bit. The output ports contain “Q1~Q4” as the output from each bit of register.


The final schematic is supposed to be as shown in the following figure.


Note the name of ports should be the exactly the same with what is shown in the schematic figure, like “clock”, “reset”, “D”, “preset”, “P1”, “P2”, “P3”, “P4”, “Q1”, “Q2”, “Q3”, “Q4”. This is done in order to be compatible with higher-level files (“shiftreg_fsm”, “shiftreg_final”, “shiftreg_s3”) in the project. The name of the ports or components can be changed by right-click the component > Rename port.


3.Add the design constraints and synthesize the design

The synthesis process translates the VHDL or schematic based design into logic gates and optimizes the architecture based on the given device type.

The constraints file in a design can be used to create timing constraints, assign pins or create area constraints. An implementation constraints file (UCF) will be created. In this experiment, the user constraints file includes pin assignment for the Spartan-3 device.


(1). To create the UCF file as another source file of the design, select the “xc3s200e-4ft256”, right-click and choose New Source as Implementation Constrains File and enter a name for the new source file in the File Name field, for instance, “shiftreg”.




(2). After the UCF file is created, it should be edited to include the pin assignment information. Right click and Run Edit Constrains by expanding User Constrains in Processes for Current Source window



Enter Design Constraints by copying and pasting the following into your user constraint file (shifereg.ucf). Note the “NET” names correspond to the ports we will have in the top-level interface file “Shiftreg_s3.vhd”. Save the constrains file.


NET "btn<0>"  LOC = "M13"  ;

NET "btn<1>"  LOC = "M14"  ;

NET "btn<2>"  LOC = "L13"  ;

NET "btn<3>"  LOC = "L14"  ;

NET "led<0>"  LOC = "K12"  ;

NET "led<1>"  LOC = "P14"  ;

NET "led<2>"  LOC = "L12"  ;

NET "led<3>"  LOC = "N14"  ;

NET "led<4>"  LOC = "P13"  ;

NET "led<5>"  LOC = "N12"  ;

NET "led<6>"  LOC = "P12"  ;

NET "led<7>"  LOC = "P11"  ;

NET "mclk"  LOC = "T9"  ;

NET "swt<0>"  LOC = "F12"  ;

NET "swt<1>"  LOC = "G12"  ;

NET "swt<2>"  LOC = "H14"  ;

NET "swt<3>"  LOC = "H13"  ;

NET "swt<4>"  LOC = "J14"  ;

NET "swt<5>"  LOC = "J13"  ;

NET "swt<6>"  LOC = "K14"  ;

NET "swt<7>"  LOC = "K13"  ;


 Another way of adding the constraint file is by clicking the project add copy of source, add the “shiftreg.ucf” in C:/EE102. And when it asks, choose to associate the “shiftreg.ucf” with “shiftreg_s3.vhd”, the top-level I/O interface file.

(3) Now, we are ready to synthesize the design. Highlight top-level entity—“shiftreg_s3.vhd”. Double click Synthesize in "Processes View" window to start the synthesis process. When this process is finished, "Completed process Synthesize" is displayed in the console window.



4. Generate the bit programming file

The Generate Programming File process is to produce a bitstream (.BIT) file for Xilinx device configuration. The (.BIT) files set switches in a programmable Xilinx FPGA chip to implement the synthesized circuit (make gates and connect them), plus device-specific information. The binary data in the BIT file can then be downloaded into the FPGA’s memory cells.


(1). In the Processes for Current Source window, Right click Generate Programming File and select Properties as the following figure.

(2). Update the Start-Up Clock to JTAG Clock under Startup options. Then click OK to close the window.


(3). At last, double click Generate Programming File to produce the bit file. The bit file is the configuration file ready to download to the FPGA chip.


5. Download the bit file to FPGA chip

 (1). Double click the Configure Device (iMPACT) in the last item in the Process window to evoke the Xilinx Programming tool. And go through the “Boundary-scan” process to let the computer find the connection to the device.


 (2). After finding the two devices on the board, click “OK”. The device showing “xc3s200” is the FPGA on the Spartan-3 board. The device with name “xcf02s” is the platform flash on the board, to which you can download program and make it non-violated. The “iMPACT” will direct you to associate the programming files to the devices. Firstly, select the bit file we just generated (should have name “Shiftreg_s3.bit”).



Then, the iMPACT will direct us to choose the “mcs” file which can associate with the platform flash. Since we didn’t generate the “mcs” file in the previous step, we will choose “Bypass”.


We will Right click the “xc3s200” and choose Program the device as in the following diagram. 

 If there is no error in the design, you'll get a successful implementation on the chip.



6. Test the design

Now, the desired design of 4-bit shift register has been configured into the FPGA chip on Spartan-3 board. We can test the design using switches and push buttons on the board. The LEDs can be used to show the outputs.


(1). Preset data defines the initial state of each shift register bit. It can be set by using switches sw3-sw0, which load initial data to shift register’s preset inputs “P4-P1”. Pushing a switch down sets the value to “0”, while pushing it up sets the value to “1”. New data can be entered to the shift register in parallel by changing the preset buttons or sequentially through the serial input “D” by setting switch 7. Push button “Btn0”-“reset” to reset register first, use “Btn1”-“preset” to load the preset data (eg. Use P4~P1=“1101”) and use button “Btn2”-“clock” to shift the data. The results will be shown by LEDs on the board.

If you preset the shift register to “1101”, then part of the results should be as shown in the following table. Please finish the rest of the table.

Clock cycle

Data in




































(2). While clocking the input, try to enter new value for “D” by flipping sw7 and observe the output.

(3). Use different preset combination and repeat step(1).



In this lab, a 4-bit shift register is implemented in a top-down schematic-based design using synthesis tool Xilinx ISE. By using the existing design of one-bit register as a component, 4-bit shift register is build though cascading components in schematic editor of Xilinx toolset. In a similar way, you can build a more complex design using components from library and wiring them together in schematic editor to obtain functional circuits. In this lab, a basic design flow of the Xilinx ISE is followed, the generated bit file is downloaded to FPGA, and then the results are verified through interface device. Xilinx Integrated Software Environment (ISE) is a very powerful and flexible integrated design environment that allows designing Xilinx FPGA and CPLD devices from start to finish. Once you get more familiar with the VHDL and hierarchical design concept, you will be ready to design and test much more complicated systems for many applications in engineering field.


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