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Avinash Kodi

Associate Professor
Electrical Engineering and Computer Science,Center for Scientific Computing and Immersive Technologies
STKR 322D
kodi@ohio.edu
Phone: 597-1481

http://oucsace.cs.ohiou.edu/~avinashk/

Avinash Karanth Kodi has been on the faculty of EECS since 2007. He has taught introductory courses in computer engineering, computer organization and advanced courses such as parallel computer architecture and interconnection networks for high-performance computing.

Dr. Kodi has published more than 60 publications in IEEE and OSA peer-reviewed conferences and journals in the field of computer architecture and optical interconnection networks. His graduate students have gone on to work at Intel Corporation, Lockheed Martin and other multinational companies. Dr. Kodi has also been the lead faculty for senior design projects involving health management system by developing hardware infrastructure for designing a health kiosk to evaluate the health of an individual.


Research Interests: Computer architecture, parallel processing, chip multiprocessors (CMPs), network-on-chips (NoCs), emerging technologies for interconnects (nanophotonics, wireless, 3D stacking) and mixed domain modeling and simulation.

All Degrees Earned: Ph.D., Electrical and Computer Engineering, University of Arizona, 2006. M.S., Electrical and Computer Engineering, University of Arizona, 2003. B.E., Electronics and Communications, Manipal Institute of Technology, Mangalore University, 2000.

Publications:

1. Randy Morris, Avinash Kodi and Ahmed Louri, “Reconfiguration of 3D Photonic On-chip Interconnects for Maximizing Performance and Improving Fault Tolerance,” 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45), Vancouver, BC, Canada, Dec 1-5, 2012.

2. Randy Morris and Avinash Kodi, “Exploring the Design of 64 & 256-core Power-Efficient Nanophotonic Interconnects,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 16, no. 5, pp. 1386-1393, September/October 2010.

3. Dominic DiTomaso, Avinash Kodi, Savas Kaya and David Matolak, “iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture”, 19th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects), Santa Clara, California, August 24-25, 2011.

4. Avinash Kodi, Ashwini Sarathy, and Ahmed Louri, “iDEAL: Inter-router Dual-function Energy- and Area-Efficient Link design for Network-on-Chip (NoC) Architecture,” Proceedings of the 35th International Symposium on Computer Architecture (ISCA-35), pp. 241-250, Beijing, China, June 21-25, 2008.

5. Avinash Kodi and Ahmed Louri, “Performance Adaptive Power-Aware Reconfigurable Optical Interconnects for HPC Systems,” Proceedings on ACM/IEEE Conference on High-Performance Networking and Computing, SuperComputing (SC’07), Reno, Nevada, November 10-16, 2007.

Awards:

NSF CAREER (2011-2016)

Journal Article, Academic Journal (27)

  • DiTomaso, D., Kodi, A., Matolak, D., Kaya, S., Laha, S., Rayess, W. A-WiNoC: Adaptive Wireless Network-on-Chip Architecture Using Energy-Efficient Transceivers. IEEE: Trans. on Parallel and Distributed Systems.
  • Laha, S., Kaya, S., Matolak, D., Rayess, W., DiTomaso, D., Kodi, A. A New Frontier in Ultra-low Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects. IEEE: IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6982195.
  • Kodi, A., Neel, B., Brantley, W. Photonic Interconnects for Exascale and Datacenter Architectures. 5. IEEE Micro Magazine; 34: 18-30. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6866037.
  • Laha, S., Kaya, S., Kodi, A., Matolak, D. A 60 GHz High Gain InGaAs pHEMT Power Amplifier with Microstrip Transmission Lines. Analog Integrated Circuits and Signal Processing.
  • Morris, R., Kodi, A., Louri, A., Whaley, R. 3D Stacked Nanophotonic Architecture with Minimal Reconfiguration. 1. IEEE Transactions on Computers; 63: 243-255. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6256662.
  • Morris, R., Jolley, E., Kodi, A. Extending the Performance and Energy-Efficiency of Nanophotonic Interconnects for Shared Memory Multicores . 1. IEEE Transactions on Parallel and Distributed Systems; 25: 83-92. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6463390.
  • Sun, J., Lysecky, R., Shankar, K., Kodi, A., Louri, A., Wang, j. Workload Assignment Considering NBTI Degradation in Multi-core Systems. 1. ACM Journal on Emerging Technologies in Computing Systems; 10: 1-22. http://dl.acm.org/citation.cfm?id=2539124.
  • DiTomaso, D., Morris, R., Kodi, A., Sarathy, A., Louri, A. Extending the Energy-Efficiency and Performance with Channel Buffers, Crossbars and Topology Analysis for NoCs. 11. IEEE Transactions on VLSI; 21: 2141-2154.
  • Matolak, D., Kaya, S., Kodi, A. Channel Modeling for Wireless Networks-on-Chips . 6. IEEE Wireless Communications Magazine; 51: 180-186.
  • Matolak, D., Kodi, A., Kaya, S., DiTomaso, D., Laha, S., Rayess, W. Wireless Networks-on-Chips: Architecture, Wireless Channel, and Devices. 5. IEEE Wireless Communications Magazine; 19: 58-65. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6339473.
  • Neel, B., Morris, R., DiTomaso, D., Kodi, A. SPRINT: Scalable Photonic Switching Fabric for High-Performance Computing (HPC). 9. IEEE/OSA Journal of Optical Communications and Networking (JOCN); 4: A37-A48.
  • Morris, R., Kodi, A. Exploring the Design of 64 & 256-core Power Efficient Nanophotonic Interconnect. 5. 16: 1386-1393.
  • Kodi, A., Louri, A. Multi-Dimension and Reconfigurable Optical Interconnects for High-Performance Computing(HPC) Systems. IEEE Journal of Lightwave Technology.
  • Kodi, A., Louri, A. Reconfigurable and Adaptive Photonic Networks for High-Performance Computing (HPC) Systems. 22. OSA Applied Optics; 44: E13-E23.
  • Kodi, A., Sarathy, A., Louri, A. Adaptive Channel Buffers in On-Chip Interconnection Networks -A Power and Performance Analysis. 9. IEEE Transactions on Computers; 57: 1169-1181.
  • Kodi, A., Louri, A. OPTISIM: A System Simulation Methodology for Optically Interconnected High-Performance Computing Systems. 5. IEEE Micro; 28: 22-36.
  • Sarathy, A., Kodi, A., Louri, A. Low-Power Low-Area Network-on-Chip Architecture using Adaptive Channel Buffers. 8. IEE Electronics Letters; 44: 512-513.
  • Kodi, A., Louri, A. A System Simulation Methodology of Optical Interconnects for High-Performance Computing(HPC) Systems. 12. OSA Journal of Optical Networking; 6: 1282-1300.
  • Kochar, C., Kodi, A., Louri, A. Proposed Low-Power High-Speed Microring Resonator-based Switching Technique for Dynamically Reconfigurable Optical Interconnects. 17. IEEE Photonics Technology Letters; 19: 1304-1306.
  • Kochar, C., Kodi, A., Louri, A. nD-RAPID: A Multi-Dimension Scalable Fault-tolerant Opto-Electronic Interconnection for Scalable High-Performance Computing Systems. 5. OSA Journal of Optical Networking, Special Issue on Photonics in Switching; 6: 465-481.
  • Kodi, A., Louri, A. RAPID for High-Performance Computing: Architecture and Performance Evaluation. 25. OSA Applied Optics, Special Issue on Information Photonics; 45: 6326-6334.
  • Kodi, A., Louri, A. Design of High-Speed Optical Interconnect for Scalable Shared Memory Multiprocessors. 1. IEEE Micro, Special Issue on Hot Interconnects; 25: 41-49.
  • Louri, A., Kodi, A. An Optical interconnection network and a modified snooping protocol for the design of Large-scale Symmetric Multiprocessors (SMPs). 12. IEEE Transactions on Parallel and Distributed Systems; 15: 1093-1104.
  • Kodi, A., Louri, A. RAPID: Reconfigurable and scalable All-Photonic Interconnect for Distributed shared memory multiprocessors. 9. IEEE/OSA Journal of Lightwave Technology, Special Issue on Optical Interconnects; 22: 2101-2110.
  • Louri, A., Kodi, A. SYMNET: An Optical Interconnection Network for Large-scale, High-Performance Symmetric Multiprocessors. 17. OSA Applied Optics; 42: 3407-3417.
  • Louri, A., Kodi, A. Parallel Optical Interconnection Network for Address Transactions in Large-scale, Cache coherent Symmetric Multiprocessors (SMPs). 2. IEEE Journal of Selected Topics in Quantum Electronics, Special Issue on Optical Interconnects; 9: 667-676.
  • Louri, A., Kodi, A. Scalable Optical Interconnection Networks for Symmetric Multiprocessors. 1. SPIE, Optics in Information Systems; 14.

Book, Chapter in Scholarly Book (1)

  • Kodi, A., Louri, A. Optical Interconnection Network for High-Performance Parallel Computers. Trivandrum: Research Signpost, Recent Research Development in Optics; 4.

Journal Article, Professional Journal (3)

  • Kodi, A., Louri, A. Introduction to the Special Issue on Network-on-Chips (NoCs). 5. Journal of Parallel and Distributed Computing; 71: 623-624.
  • Zhang, Y., Morris, R., Kodi, A. Design of a Power-Efficient Dual-Crossbar Network-on-Chip Architecture. 2. Elseiver Microprocessors and Microsystems, Embedded Hardware Design; 36: 110-118.
  • Kodi, A., Louri, A. Energy-Efficient and Bandwidth Reconfigurable Photonic Networks for High-Performance Computing (HPC) Systems. 2. IEEE Journal of Selected Topics in Quantum Electronics; 17: 384-395.

Conference Proceeding (45)

  • Laha, S., Kaya, S., Kodi, A., Matolak, D. LC Oscillators in Nanoscale DG-MOSFETs. Tampa, Florida: IEEE 15th Wireless and Microwave Technology Conference (WAMICON); 1-5. http://dx.doi.org/10.1109/WAMICON.2014.6857767.
  • DiTomaso, D., Kodi, A., Louri, A. QORE: A Fault-Tolerant Network-on-Chip Architecture with Power-Efficient Quad Function Channel (QFC) Buffer. Orlando, FL: 20th IEEE International Symposium on High-Performance Computer Architecture (HPCA).
  • Laha, S., Kaya, S., Kodi, A., Matolak, D. W-band Power Amplifier in 0.15μm InGaAs pHEMT Technology with Microstrip Transmission Lines. Bethesda, MD: 7th International Semiconductor Device Research Symposium – ISDRS.
  • Boraten, T., Kodi, A. Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures. Ashville, NC: 31st IEEE International Conference on Computer Design (ICCD); 264 - 271.
  • Kaya, S., Laha, S., DiTomaso, D., Kodi, A., Matolak, D., Rayess, W. On Ultra-Short Wireless Interconnects for NoCs and SoCs: Bridging the 'THz' Gap. Columbus, Ohio: 56th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS).
  • Morris, R., Kodi, A., Louri, A. Evaluating the Scalability and Performance of 3D Stacked Reconfigurable Nanophotonic Interconnects. Austin, TX: 15th IEEE/ACM System Level Interconnect Prediction (SLIP) colocated with Design Automation Conference (DAC).
  • DiTomaso, D., Morris, R., Jolley, E., Sarathy, A., Louri, A., Kodi, A. Energy-Efficient, Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs. Boston, Massachusetts: Workshop on High-Performance Power-Aware Computing (HPPAC), held in conjuction with IPDPS'13.
  • DiTomaso, D., Kodi, A., Matolak, D., Kaya, S., Laha, S., Rayess, W. Energy-Efficient Adaptive Wireless NoCs Architecture. Tempe, Arizona: IEEE/ACM 7th International Symposium on Networks-on-Chip (NoCs); 1-8.
  • Zhou, L., Kodi, A. PROBE: Prediction-based Optical Bandwidth Scaling for Energy-Efficient NoCs. Tempe, Arizona: IEEE/ACM 7th International Symposium on Networks-on-Chip (NoCs); 1-8.
  • Laha, S., Kaya, S., Kodi, A., Matolak, D. 60 GHz Tunable LNA in 32 nm Double Gate MOSFET for a Wireless NoC Architecture. Orlando, Florida: 14th Annual IEEE Wireless and Microwave Technology Conference (WAMICON’13); 1-4.
  • Morris, R., Kodi, A., Louri, A. Reconfiguration of 3D Photonic Network-on-Chips for Maximizing Performance and Improving Fault Tolerance. Vancouver, Canada: 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45).
  • Laha, S., Kaya, S., Kodi, A., Matolak, D. 60 GHz OOK Transmitter in 32 nm DG FinFET. Maui, Hawaii: IEEE International Conference on Wireless Information Technology and Systems.
  • Morris, R., Kodi, A., Louri, A. 3D-NoC: 3D Reconfigurable Nanophotonic Interconnects for Multicores. Montreal, Canada: 30th IEEE International Conference on Computer Design (ICCD).
  • DiTomaso, D., Laha, S., Kodi, A., Kaya, S., Matolak, D. Evaluation and Performance Analysis of Energy Efficient Wireless NoC Architecture. Boise, Idaho: 55th International Midwest Symposium on Circuits & Systems (MWSCAS).
  • DiTomaso, D., Boraten, T., Kodi, A., Louri, A. Evaluation of Fault Tolerant Channel Buffers for Improving Reliability in NoCs. Boise, Idaho: 55th International Midwest Symposium on Circuits & Systems (MWSCAS).
  • DiTomaso, D., Laha, S., Kodi, A., Kaya, S., Matolak, D. Energy-Efficient Modulation for a Wireless Network-on-Chip Architecture. Montreal, Canada: 10th IEEE International NEWCAS Conference.
  • Neel, B., Morris, R., DiTomaso, D., Kodi, A. Power-Efficient Photonic Network for Many-core Architectures. San Jose, California: Workshop on Lighter-than-Green Dependable Multicore Architectures, held in conjunction with IEEE International Green Computing Conference (IGCC-3).
  • Zhang, Y., Morris, R., DiTomaso, D., Kodi, A. Energy-Efficient, Fault-Tolerant Unified Buffer ad Bufferless Crossbar Architecture for NoCs. Shanghai, China: Workshop on High-Performance Power-Aware Computing (HPPAC), held in conjunction with IPDPS’12.
  • Laha, S., Kaya, S., Kodi, A., Matolak, D. Double Gate MOSFET Based Efficient Wide Band Tunable Power Amplifiers. Cocoa Beach, Florida: 13th Annual IEEE Wireless and Microwave Technology Conference.
  • Kodi, A., Morris, R., DiTomaso, D., Sarathy, A., Louri, A. Co-Design of Channel Buffers and Crossbar Organizations in NoCs Architecture. IEEE/ACM International Conference on Computer-Aided Design (ICCAD’11).
  • DiTomaso, D., Kodi, A., Kaya, S., Matolak, D. iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture. New Jersey: IEEE 19th Symposium on High-Performance Interconnects (Hot Interconnects); 8. http://dx.doi.org/10.1109/HOTI.2011.12.
  • Morris, R., Kodi, A. Design of a High-Speed Nanophotonic Architecture for Cache Coherent Multicores. Los Angeles, CA: Optical Fiber Communication Conference & Exposition (OFC’11); OThQ6.
  • Morris, R., Kodi, A. Scalable Nanophotonic Interconnect for Cache Coherent Multicores. Workshop on the Interaction between Nanophotonic Devices and Systems (WINDS).
  • Morris, R., Kodi, A. Design of On-Chip Networks using Mircoring Resonator Based Nanophotonic Crossbar for Future Multicores. IEEE Photonics Annual Meeting.
  • Morris, R., Kodi, A. Power-Efficient and High-Performance Multi-Level Hybrid Nanophotonic Interconnect for Multicores. IEEE/ACM Symposium on Network-on-Chips (NoCs’10); 207-214.
  • Sun, J., Lysecky, R., Shankar, K., Kodi, A., Louri, A., Wang, J. Workload Capacity Considering NBTI Degradation in Multi-core Systems. Proceedings of the IEEE 15th Asia and South Pacific Design Automation Conference (ASP-DAC'10); 450-455.
  • Kodi, A., Morris Jr, R., Louri, A., Zhang, X. On-Chip Photonic Interconnects for Scalable Multi-core Architectures. San Diego, California: 3rd ACM/IEEE International Symposium on Network-on-Chip.
  • Kodi, A., Louri, A., Wang, J. Energy-Efficient Router Buffers with Bypassing for Network-on-Chips (NoCs). San Jose, California: 10th International Symposium on Quality Electronic Design (ISQED’09); 826.
  • Jin, S., Kodi, A., Louri, A., Wang, J. NBTI Aware Workload Bal¬ancing in Multicore Systems. San Jose, California: 10th International Symposium on Quality Electronic Design (ISQED’09); 833.
  • Kodi, A., Sarathy, A., Louri, A. Adaptive Inter-Router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architecture. Yokohama: 14th Asia and South Pacific Design Automation Conference (ASP-DAC).
  • Kodi, A., Louri, A. Efficient Dynamic Bandwidth Re-allocation in Photonic Networks using SOI-based Microring Resonators. Rochester, NY: Frontiers in Optics, OSA Annual Meeting, FTuA2.
  • Kodi, A., Sarathy, A., Louri, A. iDEAL:Inter-router Dual-function Energy- and Area-Efficient Linkdesign for Network-on-Chip (NoC) Architecture. Beijing: 35th International Symposium on Computer Architecture (ISCA-35); 241-250.
  • Kodi, A., Sarathy, A., Louri, A. Design of Energy-Efficient Adaptive Channel Buffers for Network-on-Chips Architecture. Orlando, Florida: Proceedings of ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS’07).
  • Kodi, A., Louri, A. Performance Adaptive Power-Aware Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. Reno, Nevada: Proceedings of the International Conference for High-Performance Computing, Networking, Storage and Analysis (SC’07).
  • Kochar, C., Kodi, A., Louri, A. Implementation of DynamicBandwidth Re-allocation in Optical Interconnects using Microring Resonator. Stanford, California: Proceedings of 15th Annual IEEE Symposiumon High-Performance Interconnects (HotInterconnects ’07); 54-64.
  • Kodi, A., Louri, A. Power-Aware Bandwidth Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. Long Beach, California: 21st IEEE International Parallel and Distributed Processing Symposium,(IPDPS’07).
  • Kodi, A., Louri, A. A New Technique for Dynamic Bandwidth Reallocation in Optically Interconnected High-Performance Computing Systems. Stanford University, California: 14th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects 14).
  • Kodi, A., Louri, A. Switchless Photonic Architecture for Parallel Computers. Tucson, Arizona: Frontiers in Optics, 89th OSA Annual Meeting.
  • Kodi, A., Louri, A. Scalable Optical Interconnection Network for Parallel and Distributed Computing. Charlotte, North Carolina: Information Photonics, Optical Society of America.
  • Kodi, A., Louri, A. Design of a High-Speed Optical Interconnect for Scalable Shared Memory Multiprocessors. Stanford University, California: 12th Annual IEEE Symposium on High Performance Interconnects (Hot Interconnects).
  • Kodi, A., Louri, A. A Scalable Architecture for Distributed Shared Memory Multiprocessors using Optical Interconnects. Santa Fe, New Mexico: 18th International Parallel and Distributed Processing Symposium (IPDPS’04).
  • Louri, A., Kodi, A. Parallel Optical Interconnection Network for SMPs. Tucson, Arizona: Frontiers in Optics, 87th OSA Annual Meeting.
  • Louri, A., Kodi, A. Design of Large-scale Symmetric Multiprocessors (SMPs) using Parallel Optical Interconnects. Tunis: ACS/IEEE International Conference on Computer Systems and Applications, AICCSA ’03.
  • Kodi, A., Louri, A. Optical Interconnects for Large-Scale Symmetric Multiprocessor Networks. Tapei: In Proc. OSA/IEEE , Optics in Computing 2002.
  • Kodi, A., Louri, A. Y-junction Based addressing in Optical Symmetric Multiprocessor Neworks. La Jolla, San Diego: Proc. International Annual Meeting of the Lasers and Electro-Optics Society, LEOS 2001; 68-72.

Patents

  • Kodi, A., Louri, A., Sarathy, A., Wang, J. Fault-and Variation-Tolerant Energy-and Area-Efficient Links for Network-on-Chips (NoCs). OU08019.
  • Kodi, A., Louri, A., Sarathy, A., Wang, J. iDEAL:Inter-Router Dual-function Energy and Area-Efficient Links for Network-on-Chips(NoCs). UA08-078.
  • Kodi, A., DiTomaso, D., Louri, A. QORE: A Fault-Tolerant Network-on-Chip Architecture with Power-Efficient Quad Function Channel (QFC) Buffers.